30 #define QQQdialect MPLABX 44 #undef QQQMULTIPROCESSEXH 47 #define qqqMaxBranchDepth 20 48 #define QQQstructbitmap 60 #undef QQQTEMPLATEONLY 62 #define QQQUPLOADATEND 64 #undef QQQASHLINGVITRA 66 #define qqqbitmapint unsigned int 68 #undef QQQTIC2XSERIALIO 70 #undef QQQCOMPRESSED_EXH 77 #define commmodule_53zzopen zzopen 79 #define commmodule_53zqqzqz1 zqqzqz1 82 #define FILEPOINT FILE * f, 83 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 100 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 112 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 113 #ifndef LDRA_VOID_FUNC 114 #define LDRA_VOID_FUNC 117 #if defined(QQQMAINFL) 140 #ifdef QQQ_KEEPCOMMENTS 148 #if !defined(QQQSUPPRESS_UNDEF) 154 #undef QQQHITMAP_STORAGE 156 #define qqnull_params void 157 #define QQQ_PROTOTYPE_DEF 159 #undef QQ_ANSI_PROTOTYPE 161 #define QQ_ANSI_PROTOTYPE 1 164 #define QQ_ANSI_PROTOTYPE 1 170 #define ELEMENT(N) qqqbitmapint element##N; 172 #include "commmodule_53zbelem.def" 176 #define ELEMENT(N) 0, 178 #include "commmodule_53zbelem.def" 250 #ifndef _SYS_DEFINITIONS_H 251 #define _SYS_DEFINITIONS_H 260 #include "system/common/sys_common.h" 261 #include "system/common/sys_module.h" 345 #ifndef _SYSTEM_CONFIG_H 346 #define _SYSTEM_CONFIG_H 365 #define SYS_VERSION_STR "2.06" 366 #define SYS_VERSION 20600 370 #define SYS_CLK_FREQ 200000000ul 371 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 372 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 373 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 374 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 375 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 376 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 377 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 378 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 379 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 381 #define SYS_PORT_A_ANSEL 0x3F00 382 #define SYS_PORT_A_TRIS 0xFFED 383 #define SYS_PORT_A_LAT 0x0010 384 #define SYS_PORT_A_ODC 0x0000 385 #define SYS_PORT_A_CNPU 0x0020 386 #define SYS_PORT_A_CNPD 0x0000 387 #define SYS_PORT_A_CNEN 0x0021 388 #define SYS_PORT_B_ANSEL 0x10C8 389 #define SYS_PORT_B_TRIS 0x91FF 390 #define SYS_PORT_B_LAT 0x0000 391 #define SYS_PORT_B_ODC 0x0000 392 #define SYS_PORT_B_CNPU 0x0000 393 #define SYS_PORT_B_CNPD 0x0000 394 #define SYS_PORT_B_CNEN 0x0000 395 #define SYS_PORT_C_ANSEL 0xCFE1 396 #define SYS_PORT_C_TRIS 0xFFFF 397 #define SYS_PORT_C_LAT 0x0000 398 #define SYS_PORT_C_ODC 0x0000 399 #define SYS_PORT_C_CNPU 0x0000 400 #define SYS_PORT_C_CNPD 0x0000 401 #define SYS_PORT_C_CNEN 0x0000 402 #define SYS_PORT_D_ANSEL 0xC100 403 #define SYS_PORT_D_TRIS 0xFFFF 404 #define SYS_PORT_D_LAT 0x0000 405 #define SYS_PORT_D_ODC 0x0000 406 #define SYS_PORT_D_CNPU 0x0000 407 #define SYS_PORT_D_CNPD 0x0000 408 #define SYS_PORT_D_CNEN 0x0000 409 #define SYS_PORT_E_ANSEL 0xFC00 410 #define SYS_PORT_E_TRIS 0xFDFF 411 #define SYS_PORT_E_LAT 0x0000 412 #define SYS_PORT_E_ODC 0x0000 413 #define SYS_PORT_E_CNPU 0x0000 414 #define SYS_PORT_E_CNPD 0x0000 415 #define SYS_PORT_E_CNEN 0x0000 416 #define SYS_PORT_F_ANSEL 0xCEC0 417 #define SYS_PORT_F_TRIS 0xEFFF 418 #define SYS_PORT_F_LAT 0x0000 419 #define SYS_PORT_F_ODC 0x0000 420 #define SYS_PORT_F_CNPU 0x0000 421 #define SYS_PORT_F_CNPD 0x0000 422 #define SYS_PORT_F_CNEN 0x0000 423 #define SYS_PORT_G_ANSEL 0x8CBC 424 #define SYS_PORT_G_TRIS 0xDFFF 425 #define SYS_PORT_G_LAT 0x0000 426 #define SYS_PORT_G_ODC 0x0000 427 #define SYS_PORT_G_CNPU 0x0000 428 #define SYS_PORT_G_CNPD 0x0000 429 #define SYS_PORT_G_CNEN 0x0000 430 #define SYS_PORT_H_ANSEL 0x0070 431 #define SYS_PORT_H_TRIS 0xB3FB 432 #define SYS_PORT_H_LAT 0x0000 433 #define SYS_PORT_H_ODC 0x0000 434 #define SYS_PORT_H_CNPU 0x0000 435 #define SYS_PORT_H_CNPD 0x0000 436 #define SYS_PORT_H_CNEN 0x0000 437 #define SYS_PORT_J_ANSEL 0x0000 438 #define SYS_PORT_J_TRIS 0x8B7F 439 #define SYS_PORT_J_LAT 0x0080 440 #define SYS_PORT_J_ODC 0x0000 441 #define SYS_PORT_J_CNPU 0x0000 442 #define SYS_PORT_J_CNPD 0x0000 443 #define SYS_PORT_J_CNEN 0x0800 444 #define SYS_PORT_K_ANSEL 0xFF00 445 #define SYS_PORT_K_TRIS 0xFFFF 446 #define SYS_PORT_K_LAT 0x0000 447 #define SYS_PORT_K_ODC 0x0000 448 #define SYS_PORT_K_CNPU 0x0000 449 #define SYS_PORT_K_CNPD 0x0000 450 #define SYS_PORT_K_CNEN 0x0000 454 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 455 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 456 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 457 #define SYS_TMR_FREQUENCY 1000 458 #define SYS_TMR_FREQUENCY_TOLERANCE 10 459 #define SYS_TMR_UNIT_RESOLUTION 10000 460 #define SYS_TMR_CLIENT_TOLERANCE 10 461 #define SYS_TMR_INTERRUPT_NOTIFICATION false 467 #define DRV_IC_DRIVER_MODE_STATIC 470 #define DRV_SPI_NUMBER_OF_MODULES 6 473 #define DRV_SPI_POLLED 1 474 #define DRV_SPI_ISR 0 475 #define DRV_SPI_MASTER 1 476 #define DRV_SPI_SLAVE 0 478 #define DRV_SPI_EBM 1 479 #define DRV_SPI_8BIT 1 480 #define DRV_SPI_16BIT 1 481 #define DRV_SPI_32BIT 0 482 #define DRV_SPI_DMA 0 484 #define DRV_SPI_INSTANCES_NUMBER 3 485 #define DRV_SPI_CLIENTS_NUMBER 3 486 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 488 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 489 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 490 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 491 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 492 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 493 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 494 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 495 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 496 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 497 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 498 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 499 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 500 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 501 #define DRV_SPI_BAUD_RATE_IDX0 1000000 502 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 503 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 504 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 505 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 506 #define DRV_SPI_QUEUE_SIZE_IDX0 10 507 #define DRV_SPI_RESERVED_JOB_IDX0 1 509 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 510 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 511 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 512 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 513 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 514 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 515 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 516 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 517 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 518 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 519 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 520 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 521 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 522 #define DRV_SPI_BAUD_RATE_IDX1 1000000 523 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 524 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 525 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 526 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 527 #define DRV_SPI_QUEUE_SIZE_IDX1 10 528 #define DRV_SPI_RESERVED_JOB_IDX1 1 530 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 531 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 532 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 533 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 534 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 535 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 536 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 537 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 538 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 539 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 540 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 541 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 542 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 543 #define DRV_SPI_BAUD_RATE_IDX2 500000 544 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 545 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 546 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 547 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 548 #define DRV_SPI_QUEUE_SIZE_IDX2 10 549 #define DRV_SPI_RESERVED_JOB_IDX2 1 551 #define DRV_TMR_INTERRUPT_MODE true 553 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 554 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 555 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 556 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 557 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 558 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 559 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 560 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 561 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 562 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 563 #define DRV_TMR_POWER_STATE_IDX0 564 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 565 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 566 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 567 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 568 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 569 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 570 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 571 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 572 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 573 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 574 #define DRV_TMR_POWER_STATE_IDX1 576 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 577 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 578 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 579 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 580 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 581 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 582 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 583 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 584 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 585 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 586 #define DRV_TMR_POWER_STATE_IDX2 588 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 589 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 590 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 591 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 592 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 593 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 594 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 595 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 596 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 597 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 598 #define DRV_TMR_POWER_STATE_IDX3 600 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 601 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 602 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 603 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 604 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 605 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 606 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 607 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 608 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 609 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 610 #define DRV_TMR_POWER_STATE_IDX4 614 #define DRV_USART_INSTANCES_NUMBER 1 615 #define DRV_USART_CLIENTS_NUMBER 1 616 #define DRV_USART_INTERRUPT_MODE false 617 #define DRV_USART_BYTE_MODEL_SUPPORT true 618 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 619 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 627 #define DRV_USBHS_DEVICE_SUPPORT true 629 #define DRV_USBHS_HOST_SUPPORT false 631 #define DRV_USBHS_INSTANCES_NUMBER 1 633 #define DRV_USBHS_INTERRUPT_MODE true 635 #define DRV_USBHS_ENDPOINTS_NUMBER 2 638 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 640 #define USB_DEVICE_INSTANCES_NUMBER 1 642 #define USB_DEVICE_EP0_BUFFER_SIZE 64 644 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 652 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 653 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 654 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 655 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 656 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 658 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 659 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 660 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 661 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 662 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 664 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 665 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 666 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 667 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 668 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 670 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 671 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 672 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 673 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 674 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 676 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 677 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 678 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 679 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 680 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 682 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 683 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 684 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 685 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 686 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 688 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 689 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 690 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 691 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 692 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 694 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 695 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 696 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 697 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 698 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 700 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 701 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 702 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 703 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 704 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 706 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 707 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 708 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 709 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 710 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 712 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 713 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 714 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 715 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 716 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 718 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 719 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 720 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 721 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 722 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 724 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 725 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 726 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 727 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 728 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 730 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 731 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 732 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 733 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 734 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 736 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 737 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 738 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 739 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 740 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 742 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 743 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 744 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 745 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 746 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 748 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 749 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 750 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 751 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 752 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 754 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 755 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 756 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 757 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 758 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 760 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 761 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 762 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 763 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 764 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 766 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 768 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 770 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 772 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 774 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 776 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 778 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 780 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 782 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 784 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 786 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 788 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 790 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 792 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 794 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 796 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 798 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 799 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 800 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 801 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 802 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 803 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 804 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 853 #ifndef _DRV_COMMON_H 854 #define _DRV_COMMON_H 956 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 966 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 976 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1032 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1043 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1058 #define _PLIB_UNSUPPORTED 1066 #include "system/common/sys_module.h" 1078 #define DRV_IC_INDEX_0 0 1079 #define DRV_IC_INDEX_1 1 1080 #define DRV_IC_INDEX_2 2 1081 #define DRV_IC_INDEX_3 3 1082 #define DRV_IC_INDEX_4 4 1083 #define DRV_IC_INDEX_5 5 1084 #define DRV_IC_INDEX_6 6 1085 #define DRV_IC_INDEX_7 7 1086 #define DRV_IC_INDEX_8 8 1087 #define DRV_IC_INDEX_9 9 1088 #define DRV_IC_INDEX_10 10 1089 #define DRV_IC_INDEX_11 11 1090 #define DRV_IC_INDEX_12 12 1091 #define DRV_IC_INDEX_13 13 1092 #define DRV_IC_INDEX_14 14 1093 #define DRV_IC_INDEX_15 15 1125 const SYS_MODULE_INDEX index ,
1126 const SYS_MODULE_INIT *
const init ) ;
1148 const SYS_MODULE_INDEX drvIndex ,
1193 const SYS_MODULE_INDEX drvIndex ,
1326 #ifndef _DRV_IC_STATIC_H 1327 #define _DRV_IC_STATIC_H 1328 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1329 #define DRV_IC_Close( handle ) 1368 #include "system/devcon/sys_devcon.h" 1369 #include "system/clk/sys_clk.h" 1370 #include "system/int/sys_int.h" 1371 #include "system/tmr/sys_tmr.h" 1413 #ifndef _DRV_ADC_STATIC_H 1414 #define _DRV_ADC_STATIC_H 1415 #include <stdbool.h> 1416 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1417 #include "peripheral/adchs/plib_adchs.h" 1418 #include "peripheral/int/plib_int.h" 1458 uint8_t bufIndex ) ;
1462 uint8_t bufIndex ) ;
1512 #ifndef _DRV_TMR_STATIC_H 1513 #define _DRV_TMR_STATIC_H 1562 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1563 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1564 #include "peripheral/tmr/plib_tmr.h" 1600 #ifndef _TMR_DEFINITIONS_PIC32M_H 1601 #define _TMR_DEFINITIONS_PIC32M_H 1659 #include "system/int/sys_int.h" 1660 #include "system/clk/sys_clk.h" 1679 #define DRV_TMR_INDEX_0 0 1680 #define DRV_TMR_INDEX_1 1 1681 #define DRV_TMR_INDEX_2 2 1682 #define DRV_TMR_INDEX_3 3 1683 #define DRV_TMR_INDEX_4 4 1684 #define DRV_TMR_INDEX_5 5 1685 #define DRV_TMR_INDEX_6 6 1686 #define DRV_TMR_INDEX_7 7 1687 #define DRV_TMR_INDEX_8 8 1688 #define DRV_TMR_INDEX_9 9 1689 #define DRV_TMR_INDEX_10 10 1690 #define DRV_TMR_INDEX_11 11 1701 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1786 uint32_t dividerMin ;
1788 uint32_t dividerMax ;
1791 uint32_t dividerStep ;
1807 SYS_MODULE_INIT moduleInit ;
1809 TMR_MODULE_ID tmrId ;
1813 TMR_PRESCALE prescale ;
1817 INT_SOURCE interruptSource ;
1825 bool asyncWriteEnable ;
1840 uint32_t alarmCount ) ;
1902 const SYS_MODULE_INDEX drvIndex ,
1903 const SYS_MODULE_INIT *
const init ) ;
1943 SYS_MODULE_OBJ
object ) ;
1990 SYS_MODULE_OBJ
object ) ;
2024 SYS_MODULE_OBJ
object ) ;
2078 const SYS_MODULE_INDEX index ,
2179 uint32_t counterPeriod ) ;
2669 TMR_PRESCALE preScale ) ;
2909 #ifndef _DRV_TMR_DEPRECATED_H 2910 #define _DRV_TMR_DEPRECATED_H 2951 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3015 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3080 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3139 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3200 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3259 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3320 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3350 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3382 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3413 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3445 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3507 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3572 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3589 #include "peripheral/tmr/plib_tmr.h" 3590 #include "peripheral/int/plib_int.h" 3592 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3594 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3596 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3598 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3617 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3623 static inline SYS_STATUS
3626 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3637 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3648 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3658 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3667 TMR_PRESCALE prescale ) ;
3698 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3727 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3733 static inline SYS_STATUS
3736 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3747 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3758 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3768 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3777 TMR_PRESCALE prescale ) ;
3808 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3837 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3843 static inline SYS_STATUS
3846 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3857 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3868 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3878 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3887 TMR_PRESCALE prescale ) ;
3918 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3947 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3953 static inline SYS_STATUS
3956 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3967 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3978 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3988 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
3997 TMR_PRESCALE prescale ) ;
4028 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4057 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4063 static inline SYS_STATUS
4066 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4077 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4088 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4098 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4107 TMR_PRESCALE prescale ) ;
4138 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4157 #include "peripheral/int/plib_int.h" 4199 #ifndef _DRV_PMP_STATIC_H 4200 #define _DRV_PMP_STATIC_H 4201 #include "peripheral/pmp/plib_pmp.h" 4216 PMP_DATA_WAIT_STATES dataWait ,
4217 PMP_STROBE_WAIT_STATES strobeWait ,
4218 PMP_DATA_HOLD_STATES dataHold ) ;
4273 #ifndef _DRV_USART_STATIC_H 4274 #define _DRV_USART_STATIC_H 4313 #ifndef _DRV_USART_STATIC_LOCAL_H 4314 #define _DRV_USART_STATIC_LOCAL_H 4321 #include <stdbool.h> 4358 #ifndef _DRV_USART_H 4359 #define _DRV_USART_H 4399 #ifndef _DRV_USART_DEFINITIONS_H 4400 #define _DRV_USART_DEFINITIONS_H 4406 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4407 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4444 #ifndef _PLIB_USART_H 4445 #define _PLIB_USART_H 4488 #ifndef _USART_PROCESSOR_H 4489 #define _USART_PROCESSOR_H 4498 #include <stdbool.h> 4499 #error "No Processor Family specified" 4543 USART_MODULE_ID index ) ;
4573 USART_MODULE_ID index ) ;
4605 USART_MODULE_ID index ) ;
4639 USART_MODULE_ID index ,
4640 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4669 USART_BRG_CLOCK_SOURCE
4671 USART_MODULE_ID index ) ;
4725 USART_MODULE_ID index ) ;
4755 USART_MODULE_ID index ) ;
4784 USART_MODULE_ID index ) ;
4816 USART_MODULE_ID index ) ;
4847 USART_MODULE_ID index ) ;
4889 USART_MODULE_ID index ) ;
4922 USART_MODULE_ID index ) ;
4954 USART_MODULE_ID index ) ;
4995 USART_MODULE_ID index ,
4996 uint32_t clockFrequency ,
4997 uint32_t baudRate ) ;
5038 USART_MODULE_ID index ,
5039 uint32_t clockFrequency ,
5040 uint32_t baudRate ) ;
5073 USART_MODULE_ID index ,
5074 int32_t clockFrequency ) ;
5109 USART_MODULE_ID index ,
5144 USART_MODULE_ID index ) ;
5179 USART_MODULE_ID index ,
5214 USART_MODULE_ID index ) ;
5246 USART_MODULE_ID index ) ;
5280 USART_MODULE_ID index ) ;
5313 USART_MODULE_ID index ) ;
5346 USART_MODULE_ID index ) ;
5380 USART_MODULE_ID index ,
5425 USART_MODULE_ID index ) ;
5459 USART_MODULE_ID index ) ;
5495 USART_MODULE_ID index ) ;
5532 USART_MODULE_ID index ,
5572 USART_MODULE_ID index ) ;
5610 USART_MODULE_ID index ) ;
5645 USART_MODULE_ID index ) ;
5679 USART_MODULE_ID index ) ;
5713 USART_MODULE_ID index ) ;
5746 USART_MODULE_ID index ) ;
5778 USART_MODULE_ID index ) ;
5810 USART_MODULE_ID index ) ;
5843 USART_MODULE_ID index ) ;
5877 USART_MODULE_ID index ) ;
5906 USART_MODULE_ID index ) ;
5935 USART_MODULE_ID index ) ;
5967 USART_MODULE_ID index ) ;
5999 USART_MODULE_ID index ) ;
6029 USART_MODULE_ID index ) ;
6059 USART_MODULE_ID index ) ;
6088 USART_MODULE_ID index ) ;
6117 USART_MODULE_ID index ) ;
6151 USART_MODULE_ID index ,
6152 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6184 USART_MODULE_ID index ,
6185 USART_RECEIVE_INTR_MODE interruptMode ) ;
6218 USART_MODULE_ID index ,
6219 USART_LINECONTROL_MODE dataFlowConfig ) ;
6252 USART_MODULE_ID index ,
6253 USART_HANDSHAKE_MODE handshakeConfig ) ;
6286 USART_MODULE_ID index ,
6317 USART_MODULE_ID index ) ;
6346 USART_MODULE_ID index ) ;
6377 USART_MODULE_ID index ) ;
6408 USART_MODULE_ID index ) ;
6438 USART_MODULE_ID index ) ;
6470 USART_MODULE_ID index ,
6471 USART_OPERATION_MODE operationmode ) ;
6501 USART_MODULE_ID index ) ;
6534 USART_MODULE_ID index ) ;
6563 USART_MODULE_ID index ) ;
6593 USART_MODULE_ID index ) ;
6629 USART_MODULE_ID index ) ;
6680 USART_MODULE_ID index ,
6683 bool wakeFromSleep ,
6728 USART_MODULE_ID index ,
6729 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6730 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6731 USART_OPERATION_MODE operationMode ) ;
6777 USART_MODULE_ID index ,
6778 uint32_t systemClock ,
6824 USART_MODULE_ID index ) ;
6845 USART_MODULE_ID index ) ;
6866 USART_MODULE_ID index ) ;
6900 USART_MODULE_ID index ) ;
6927 USART_MODULE_ID index ) ;
6953 USART_MODULE_ID index ) ;
6980 USART_MODULE_ID index ) ;
7006 USART_MODULE_ID index ) ;
7031 USART_MODULE_ID index ) ;
7057 USART_MODULE_ID index ) ;
7082 USART_MODULE_ID index ) ;
7108 USART_MODULE_ID index ) ;
7133 USART_MODULE_ID index ) ;
7159 USART_MODULE_ID index ) ;
7186 USART_MODULE_ID index ) ;
7212 USART_MODULE_ID index ) ;
7238 USART_MODULE_ID index ) ;
7265 USART_MODULE_ID index ) ;
7292 USART_MODULE_ID index ) ;
7319 USART_MODULE_ID index ) ;
7345 USART_MODULE_ID index ) ;
7370 USART_MODULE_ID index ) ;
7396 USART_MODULE_ID index ) ;
7423 USART_MODULE_ID index ) ;
7449 USART_MODULE_ID index ) ;
7475 USART_MODULE_ID index ) ;
7500 USART_MODULE_ID index ) ;
7525 USART_MODULE_ID index ) ;
7550 USART_MODULE_ID index ) ;
7576 USART_MODULE_ID index ) ;
7601 USART_MODULE_ID index ) ;
7627 USART_MODULE_ID index ) ;
7653 USART_MODULE_ID index ) ;
7678 USART_MODULE_ID index ) ;
7704 USART_MODULE_ID index ) ;
7729 USART_MODULE_ID index ) ;
7754 USART_MODULE_ID index ) ;
7781 USART_MODULE_ID index ) ;
7806 USART_MODULE_ID index ) ;
7832 USART_MODULE_ID index ) ;
7897 #include "system/common/sys_common.h" 7898 #include "system/common/sys_module.h" 7910 #include "system/int/sys_int.h" 7982 #ifndef _SYS_DMA_DEFINITIONS_H 7983 #define _SYS_DMA_DEFINITIONS_H 7989 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7990 #include "system/common/sys_common.h" 7991 #include "system/common/sys_module.h" 8061 #ifndef _PLIB_DMA_PROCESSOR_H 8062 #define _PLIB_DMA_PROCESSOR_H 8063 #error "Can't find header" 8107 DMA_MODULE_ID index ,
8108 DMA_CHANNEL channel ) ;
8142 DMA_MODULE_ID index ,
8143 DMA_CHANNEL channel ,
8144 DMA_CHANNEL_COLLISION collisonType ) ;
8176 DMA_MODULE_ID index ,
8177 DMA_CHANNEL channel ) ;
8209 DMA_MODULE_ID index ,
8210 DMA_CHANNEL channel ) ;
8248 DMA_MODULE_ID index ,
8249 DMA_CHANNEL channel ,
8250 DMA_CHANNEL_PRIORITY channelPriority ) ;
8279 DMA_CHANNEL_PRIORITY
8281 DMA_MODULE_ID index ,
8282 DMA_CHANNEL channel ) ;
8310 DMA_MODULE_ID index ,
8311 DMA_CHANNEL_PRIORITY channelPriority ) ;
8336 DMA_CHANNEL_PRIORITY
8338 DMA_MODULE_ID index ) ;
8368 DMA_MODULE_ID index ,
8369 DMA_CHANNEL channel ) ;
8400 DMA_MODULE_ID index ,
8401 DMA_CHANNEL channel ) ;
8430 DMA_MODULE_ID index ,
8431 DMA_CHANNEL channel ) ;
8460 DMA_MODULE_ID index ,
8461 DMA_CHANNEL channel ) ;
8492 DMA_MODULE_ID index ,
8493 DMA_CHANNEL channel ) ;
8522 DMA_MODULE_ID index ,
8523 DMA_CHANNEL channel ) ;
8554 DMA_MODULE_ID index ,
8555 DMA_CHANNEL channel ) ;
8586 DMA_MODULE_ID index ,
8587 DMA_CHANNEL channel ) ;
8616 DMA_MODULE_ID index ,
8617 DMA_CHANNEL channel ) ;
8648 DMA_MODULE_ID index ,
8649 DMA_CHANNEL channel ) ;
8678 DMA_MODULE_ID index ,
8679 DMA_CHANNEL channel ) ;
8709 DMA_MODULE_ID index ,
8710 DMA_CHANNEL channel ) ;
8740 DMA_MODULE_ID index ,
8741 DMA_CHANNEL channel ) ;
8771 DMA_MODULE_ID index ,
8772 DMA_CHANNEL channel ) ;
8802 DMA_MODULE_ID index ,
8803 DMA_CHANNEL channel ) ;
8834 DMA_MODULE_ID index ,
8835 DMA_CHANNEL channel ) ;
8866 DMA_MODULE_ID index ,
8867 DMA_CHANNEL channel ,
8868 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8897 DMA_CHANNEL_TRANSFER_DIRECTION
8899 DMA_MODULE_ID index ,
8900 DMA_CHANNEL channel ) ;
8936 DMA_MODULE_ID index ,
8937 DMA_CHANNEL channel ,
8939 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8972 DMA_MODULE_ID index ,
8973 DMA_CHANNEL channel ,
8974 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9005 DMA_MODULE_ID index ,
9006 DMA_CHANNEL channel ,
9007 uint16_t peripheraladdress ) ;
9035 DMA_MODULE_ID index ,
9036 DMA_CHANNEL channel ) ;
9067 DMA_MODULE_ID index ,
9068 DMA_CHANNEL channel ,
9069 uint16_t transferCount ) ;
9097 DMA_MODULE_ID index ,
9098 DMA_CHANNEL channel ) ;
9131 DMA_MODULE_ID index ,
9132 DMA_CHANNEL channel ,
9133 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9161 DMA_SOURCE_ADDRESSING_MODE
9163 DMA_MODULE_ID index ,
9164 DMA_CHANNEL channel ) ;
9197 DMA_MODULE_ID index ,
9198 DMA_CHANNEL channel ,
9199 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9228 DMA_DESTINATION_ADDRESSING_MODE
9230 DMA_MODULE_ID index ,
9231 DMA_CHANNEL channel ) ;
9264 DMA_MODULE_ID index ,
9265 DMA_CHANNEL channel ,
9266 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9294 DMA_CHANNEL_ADDRESSING_MODE
9296 DMA_MODULE_ID index ,
9297 DMA_CHANNEL channel ) ;
9335 DMA_MODULE_ID index ,
9336 DMA_CHANNEL channel ,
9337 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9373 DMA_MODULE_ID index ,
9374 DMA_CHANNEL channel ,
9375 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9410 DMA_MODULE_ID index ,
9411 DMA_CHANNEL channel ,
9412 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9441 DMA_CHANNEL_INT_SOURCE
9443 DMA_MODULE_ID index ,
9444 DMA_CHANNEL channel ) ;
9479 DMA_MODULE_ID index ,
9480 DMA_CHANNEL channel ,
9481 DMA_TRIGGER_SOURCE IRQnum ) ;
9516 DMA_MODULE_ID index ,
9517 DMA_CHANNEL channel ,
9518 DMA_TRIGGER_SOURCE IRQ ) ;
9549 DMA_MODULE_ID index ,
9550 DMA_CHANNEL channel ,
9551 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9578 DMA_CHANNEL_DATA_SIZE
9580 DMA_MODULE_ID index ,
9581 DMA_CHANNEL channel ) ;
9615 DMA_MODULE_ID index ,
9616 DMA_CHANNEL channel ,
9617 DMA_TRANSFER_MODE channeltransferMode ) ;
9649 DMA_MODULE_ID index ,
9650 DMA_CHANNEL channel ) ;
9679 DMA_MODULE_ID index ,
9680 DMA_CHANNEL channel ) ;
9710 DMA_MODULE_ID index ,
9711 DMA_CHANNEL channel ) ;
9740 DMA_MODULE_ID index ,
9741 DMA_CHANNEL channel ) ;
9769 DMA_MODULE_ID index ,
9770 DMA_CHANNEL channel ) ;
9800 DMA_MODULE_ID index ,
9801 DMA_CHANNEL channel ) ;
9828 DMA_MODULE_ID index ,
9829 DMA_CHANNEL channel ) ;
9865 DMA_MODULE_ID index ,
9866 DMA_CHANNEL channel ) ;
9897 DMA_MODULE_ID index ,
9898 DMA_CHANNEL channel ) ;
9931 DMA_MODULE_ID index ) ;
9960 DMA_MODULE_ID index ) ;
9990 DMA_MODULE_ID index ) ;
10019 DMA_MODULE_ID index ) ;
10048 DMA_MODULE_ID index ) ;
10078 DMA_MODULE_ID index ) ;
10106 DMA_MODULE_ID index ) ;
10134 DMA_MODULE_ID index ) ;
10162 DMA_MODULE_ID index ) ;
10191 DMA_MODULE_ID index ) ;
10219 DMA_MODULE_ID index ) ;
10253 DMA_MODULE_ID index ) ;
10283 DMA_MODULE_ID index ) ;
10313 DMA_MODULE_ID index ) ;
10342 DMA_MODULE_ID index ) ;
10377 DMA_MODULE_ID index ,
10378 DMA_CHANNEL channel ) ;
10407 DMA_MODULE_ID index ) ;
10439 DMA_MODULE_ID index ,
10440 DMA_CRC_TYPE CRCType ) ;
10471 DMA_MODULE_ID index ) ;
10501 DMA_MODULE_ID index ) ;
10531 DMA_MODULE_ID index ) ;
10561 DMA_MODULE_ID index ) ;
10590 DMA_MODULE_ID index ) ;
10620 DMA_MODULE_ID index ) ;
10649 DMA_MODULE_ID index ) ;
10679 DMA_MODULE_ID index ,
10680 uint8_t polyLength ) ;
10709 DMA_MODULE_ID index ) ;
10738 DMA_MODULE_ID index ,
10739 DMA_CRC_BIT_ORDER bitOrder ) ;
10770 DMA_MODULE_ID index ) ;
10799 DMA_MODULE_ID index ) ;
10829 DMA_MODULE_ID index ,
10830 DMA_CRC_BYTE_ORDER byteOrder ) ;
10859 DMA_MODULE_ID index ) ;
10890 DMA_MODULE_ID index ) ;
10922 DMA_MODULE_ID index ,
10923 uint32_t DMACRCdata ) ;
10954 DMA_MODULE_ID index ) ;
10987 DMA_MODULE_ID index ,
10988 uint32_t DMACRCXOREnableMask ) ;
11026 DMA_MODULE_ID index ,
11027 DMA_CHANNEL dmaChannel ) ;
11064 DMA_MODULE_ID index ,
11065 DMA_CHANNEL dmaChannel ,
11066 uint32_t sourceStartAddress ) ;
11100 DMA_MODULE_ID index ,
11101 DMA_CHANNEL dmaChannel ) ;
11139 DMA_MODULE_ID index ,
11140 DMA_CHANNEL dmaChannel ,
11141 uint32_t destinationStartAddress ) ;
11181 DMA_MODULE_ID index ,
11182 DMA_CHANNEL dmaChannel ) ;
11221 DMA_MODULE_ID index ,
11222 DMA_CHANNEL dmaChannel ,
11223 uint16_t sourceSize ) ;
11258 DMA_MODULE_ID index ,
11259 DMA_CHANNEL dmaChannel ) ;
11296 DMA_MODULE_ID index ,
11297 DMA_CHANNEL dmaChannel ,
11298 uint16_t destinationSize ) ;
11332 DMA_MODULE_ID index ,
11333 DMA_CHANNEL dmaChannel ) ;
11368 DMA_MODULE_ID index ,
11369 DMA_CHANNEL dmaChannel ) ;
11404 DMA_MODULE_ID index ,
11405 DMA_CHANNEL dmaChannel ) ;
11442 DMA_MODULE_ID index ,
11443 DMA_CHANNEL dmaChannel ,
11444 uint16_t CellSize ) ;
11478 DMA_MODULE_ID index ,
11479 DMA_CHANNEL dmaChannel ) ;
11516 DMA_MODULE_ID index ,
11517 DMA_CHANNEL dmaChannel ) ;
11556 DMA_MODULE_ID index ,
11557 DMA_CHANNEL dmaChannel ,
11558 uint16_t patternData ) ;
11602 DMA_MODULE_ID index ,
11603 DMA_CHANNEL dmaChannel ,
11604 DMA_INT_TYPE dmaINTSource ) ;
11639 DMA_MODULE_ID index ,
11640 DMA_CHANNEL dmaChannel ,
11641 DMA_INT_TYPE dmaINTSource ) ;
11677 DMA_MODULE_ID index ,
11678 DMA_CHANNEL dmaChannel ,
11679 DMA_INT_TYPE dmaINTSource ) ;
11713 DMA_MODULE_ID index ,
11714 DMA_CHANNEL dmaChannel ,
11715 DMA_INT_TYPE dmaINTSource ) ;
11749 DMA_MODULE_ID index ,
11750 DMA_CHANNEL dmaChannel ,
11751 DMA_INT_TYPE dmaINTSource ) ;
11789 DMA_MODULE_ID index ,
11790 DMA_CHANNEL dmaChannel ,
11791 DMA_INT_TYPE dmaINTSource ) ;
11824 DMA_MODULE_ID index ,
11825 DMA_CHANNEL dmaChannel ,
11826 DMA_PATTERN_LENGTH patternLen ) ;
11859 DMA_MODULE_ID index ,
11860 DMA_CHANNEL dmaChannel ) ;
11890 DMA_MODULE_ID index ,
11891 DMA_CHANNEL channel ) ;
11924 DMA_MODULE_ID index ,
11925 DMA_CHANNEL channel ) ;
11955 DMA_MODULE_ID index ,
11956 DMA_CHANNEL channel ) ;
11988 DMA_MODULE_ID index ,
11989 DMA_CHANNEL channel ,
11990 uint8_t pattern ) ;
12021 DMA_MODULE_ID index ,
12022 DMA_CHANNEL channel ) ;
12054 DMA_MODULE_ID index ) ;
12079 DMA_MODULE_ID index ) ;
12103 DMA_MODULE_ID index ) ;
12128 DMA_MODULE_ID index ) ;
12151 DMA_MODULE_ID index ) ;
12175 DMA_MODULE_ID index ) ;
12198 DMA_MODULE_ID index ) ;
12222 DMA_MODULE_ID index ) ;
12246 DMA_MODULE_ID index ) ;
12271 DMA_MODULE_ID index ) ;
12295 DMA_MODULE_ID index ) ;
12319 DMA_MODULE_ID index ) ;
12342 DMA_MODULE_ID index ) ;
12366 DMA_MODULE_ID index ) ;
12390 DMA_MODULE_ID index ) ;
12414 DMA_MODULE_ID index ) ;
12438 DMA_MODULE_ID index ) ;
12462 DMA_MODULE_ID index ) ;
12485 DMA_MODULE_ID index ) ;
12510 DMA_MODULE_ID index ) ;
12535 DMA_MODULE_ID index ) ;
12559 DMA_MODULE_ID index ) ;
12584 DMA_MODULE_ID index ) ;
12608 DMA_MODULE_ID index ) ;
12632 DMA_MODULE_ID index ) ;
12658 DMA_MODULE_ID index ) ;
12683 DMA_MODULE_ID index ) ;
12707 DMA_MODULE_ID index ) ;
12732 DMA_MODULE_ID index ) ;
12755 DMA_MODULE_ID index ) ;
12778 DMA_MODULE_ID index ) ;
12801 DMA_MODULE_ID index ) ;
12824 DMA_MODULE_ID index ) ;
12849 DMA_MODULE_ID index ) ;
12874 DMA_MODULE_ID index ) ;
12898 DMA_MODULE_ID index ) ;
12923 DMA_MODULE_ID index ) ;
12947 DMA_MODULE_ID index ) ;
12971 DMA_MODULE_ID index ) ;
12994 DMA_MODULE_ID index ) ;
13017 DMA_MODULE_ID index ) ;
13041 DMA_MODULE_ID index ) ;
13065 DMA_MODULE_ID index ) ;
13089 DMA_MODULE_ID index ) ;
13116 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13129 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13142 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13172 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13346 DMA_CRC_TYPE type ;
13352 uint8_t polyLength ;
13355 DMA_CRC_BIT_ORDER bitOrder ;
13358 DMA_CRC_BYTE_ORDER byteOrder ;
13368 uint32_t xorBitMask ;
13493 SYS_MODULE_OBJ
object ,
13494 DMA_CHANNEL activeChannel ) ;
13497 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13542 uintptr_t contextHandle ) ;
13588 const SYS_MODULE_INIT *
const init ) ;
13639 DMA_CHANNEL channel ) ;
13725 DMA_TRIGGER_SOURCE eventSrc ) ;
13803 DMA_PATTERN_LENGTH length ,
13805 uint8_t ignorePattern ) ;
14058 const void * srcAddr ,
14060 const void * destAddr ,
14062 size_t cellSize ) ;
14159 const void * srcAddr ,
14161 const void * destAddr ,
14163 size_t cellSize ) ;
14359 const uintptr_t contextHandle ) ;
14655 DMA_TRIGGER_SOURCE eventSrc ) ;
14834 SYS_MODULE_OBJ
object ,
14835 DMA_CHANNEL activeChannel ) ;
14845 SYS_MODULE_OBJ
object ) ;
14855 SYS_MODULE_OBJ
object ,
14856 DMA_CHANNEL activeChannel ) ;
14883 #define DRV_USART_INDEX_0 0 14884 #define DRV_USART_INDEX_1 1 14885 #define DRV_USART_INDEX_2 2 14886 #define DRV_USART_INDEX_3 3 14887 #define DRV_USART_INDEX_4 4 14888 #define DRV_USART_INDEX_5 5 14902 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14913 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14924 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14958 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15109 uintptr_t context ) ;
15157 USART_HANDSHAKE_MODE_FLOW_CONTROL
15161 USART_HANDSHAKE_MODE_SIMPLEX
15323 } AddressedModeInit ;
15348 = USART_ERROR_PARITY
15353 = USART_ERROR_FRAMING
15358 = USART_ERROR_RECEIVER_OVERRUN
15440 SYS_MODULE_INIT moduleInit ;
15444 USART_MODULE_ID usartID ;
15462 uint32_t brgClock ;
15478 USART_OPERATION_MODE linesEnable ;
15482 INT_SOURCE interruptTransmit ;
15486 INT_SOURCE interruptReceive ;
15490 INT_SOURCE interruptError ;
15495 unsigned int queueSizeReceive ;
15500 unsigned int queueSizeTransmit ;
15504 DMA_CHANNEL dmaChannelTransmit ;
15508 DMA_CHANNEL dmaChannelReceive ;
15512 INT_SOURCE dmaInterruptTransmit ;
15516 INT_SOURCE dmaInterruptReceive ;
15600 const SYS_MODULE_INDEX index ,
15601 const SYS_MODULE_INIT *
const init ) ;
15639 SYS_MODULE_OBJ
object ) ;
15677 SYS_MODULE_OBJ
object ) ;
15718 SYS_MODULE_OBJ
object ) ;
15759 SYS_MODULE_OBJ
object ) ;
15800 SYS_MODULE_OBJ
object ) ;
15879 const SYS_MODULE_INDEX index ,
16063 const size_t size ) ;
16256 const size_t size ) ;
16344 const uintptr_t context ) ;
16611 const size_t numbytes ) ;
16679 const size_t numbytes ) ;
16816 const uint8_t byte ) ;
17034 const SYS_MODULE_INDEX index ,
17087 const SYS_MODULE_INDEX index ,
17136 const SYS_MODULE_INDEX index ,
17351 #ifndef _DRV_USART_FEATURE_MAPPING_H 17352 #define _DRV_USART_FEATURE_MAPPING_H 17361 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17362 #define _DRV_USART_InterruptSourceEnable( source ) 17363 #define _DRV_USART_InterruptSourceDisable( source ) false 17364 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17365 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17366 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17367 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17368 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17371 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17380 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17381 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17382 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17383 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17384 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17397 #include "system/clk/sys_clk.h" 17398 #include "system/int/sys_int.h" 17436 #ifndef _SYS_DEBUG_H 17437 #define _SYS_DEBUG_H 17438 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17441 #define SYS_DEBUG_BUFFER_DMA_READY 17491 #define SYS_DEBUG_INDEX_0 0 17507 SYS_MODULE_INIT moduleInit ;
17511 SYS_MODULE_INDEX consoleIndex ;
17559 const SYS_MODULE_INDEX index ,
17560 const SYS_MODULE_INIT *
const init ) ;
17600 SYS_MODULE_OBJ
object ,
17601 const SYS_MODULE_INIT *
const init ) ;
17631 SYS_MODULE_OBJ
object ) ;
17664 SYS_MODULE_OBJ
object ) ;
17708 SYS_MODULE_OBJ
object ) ;
17751 const char * message ) ;
17801 const char * format ,
17891 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17935 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17978 #define SYS_MESSAGE( message ) 18011 #define SYS_DEBUG_MESSAGE( level , message ) 18058 #define SYS_PRINT( fmt ,... ) 18106 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18131 #define SYS_DEBUG_BreakPoint( ) 18140 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18141 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18142 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18159 #define _DRV_USART_RX_DEPTH 9 18225 const SYS_MODULE_INDEX index ,
18250 const uint8_t byte ) ;
18321 #ifndef _SYS_PORTS_H 18322 #define _SYS_PORTS_H 18361 #ifndef _SYS_PORTS_DEFINITIONS_H 18362 #define _SYS_PORTS_DEFINITIONS_H 18368 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18369 #include "system/common/sys_common.h" 18370 #include "system/common/sys_module.h" 18407 #ifndef _PLIB_PORTS_H 18408 #define _PLIB_PORTS_H 18409 #include <stdint.h> 18410 #include <stddef.h> 18475 #ifndef _PLIB_PORTS_PROCESSOR_H 18476 #define _PLIB_PORTS_PROCESSOR_H 18477 #error "Can't find header" 18527 PORTS_MODULE_ID index ,
18528 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18529 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18572 PORTS_MODULE_ID index ,
18573 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18574 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18609 PORTS_MODULE_ID index ,
18610 PORTS_ANALOG_PIN pin ,
18611 PORTS_PIN_MODE mode ) ;
18651 PORTS_MODULE_ID index ,
18652 PORTS_CHANNEL channel ,
18653 PORTS_BIT_POS bitPos ,
18654 PORTS_PIN_MODE mode ) ;
18689 PORTS_MODULE_ID index ,
18690 PORTS_CHANNEL channel ,
18691 PORTS_BIT_POS bitPos ) ;
18725 PORTS_MODULE_ID index ,
18726 PORTS_CHANNEL channel ,
18727 PORTS_BIT_POS bitPos ) ;
18764 PORTS_MODULE_ID index ,
18765 PORTS_CHANNEL channel ,
18766 PORTS_BIT_POS bitPos ) ;
18807 PORTS_MODULE_ID index ,
18808 PORTS_CHANNEL channel ,
18809 PORTS_BIT_POS bitPos ) ;
18848 PORTS_MODULE_ID index ,
18849 PORTS_CHANNEL channel ,
18850 PORTS_BIT_POS bitPos ) ;
18888 PORTS_MODULE_ID index ,
18889 PORTS_CHANNEL channel ,
18890 PORTS_BIT_POS bitPos ) ;
18925 PORTS_MODULE_ID index ,
18926 PORTS_CHANNEL channel ) ;
18961 PORTS_MODULE_ID index ,
18962 PORTS_CHANNEL channel ) ;
18999 PORTS_MODULE_ID index ,
19000 PORTS_CHANNEL channel ) ;
19037 PORTS_MODULE_ID index ,
19038 PORTS_CHANNEL channel ) ;
19075 PORTS_MODULE_ID index ,
19076 PORTS_CHANNEL channel ,
19077 PORTS_BIT_POS bitPos ) ;
19114 PORTS_MODULE_ID index ,
19115 PORTS_CHANNEL channel ,
19116 PORTS_BIT_POS bitPos ) ;
19154 PORTS_MODULE_ID index ,
19155 PORTS_CHANNEL channel ,
19156 PORTS_BIT_POS bitPos ) ;
19193 PORTS_MODULE_ID index ,
19194 PORTS_CHANNEL channel ,
19195 PORTS_BIT_POS bitPos ,
19230 PORTS_MODULE_ID index ,
19231 PORTS_CHANNEL channel ,
19232 PORTS_BIT_POS bitPos ) ;
19266 PORTS_MODULE_ID index ,
19267 PORTS_CHANNEL channel ,
19268 PORTS_BIT_POS bitPos ) ;
19302 PORTS_MODULE_ID index ,
19303 PORTS_CHANNEL channel ,
19304 PORTS_BIT_POS bitPos ) ;
19339 PORTS_MODULE_ID index ,
19340 PORTS_CHANNEL channel ,
19341 PORTS_BIT_POS bitPos ) ;
19376 PORTS_MODULE_ID index ,
19377 PORTS_CHANNEL channel ,
19378 PORTS_BIT_POS bitPos ) ;
19412 PORTS_MODULE_ID index ,
19413 PORTS_CHANNEL channel ,
19414 PORTS_BIT_POS bitPos ) ;
19448 PORTS_MODULE_ID index ,
19449 PORTS_CHANNEL channel ,
19450 PORTS_BIT_POS bitPos ) ;
19488 PORTS_MODULE_ID index ,
19489 PORTS_CHANNEL channel ) ;
19523 PORTS_MODULE_ID index ,
19524 PORTS_CHANNEL channel ) ;
19558 PORTS_MODULE_ID index ,
19559 PORTS_CHANNEL channel ,
19602 PORTS_MODULE_ID index ,
19603 PORTS_CHANNEL channel ,
19639 PORTS_MODULE_ID index ,
19640 PORTS_CHANNEL channel ,
19675 PORTS_MODULE_ID index ,
19676 PORTS_CHANNEL channel ,
19712 PORTS_MODULE_ID index ,
19713 PORTS_CHANNEL channel ,
19748 PORTS_MODULE_ID index ,
19749 PORTS_CHANNEL channel ,
19782 PORTS_MODULE_ID index ,
19783 PORTS_CHANNEL channel ) ;
19817 PORTS_MODULE_ID index ,
19818 PORTS_CHANNEL channel ,
19854 PORTS_MODULE_ID index ,
19855 PORTS_CHANNEL channel ,
19901 PORTS_MODULE_ID index ,
19902 PORTS_CHANNEL channel ,
19904 PORTS_PIN_MODE mode ) ;
19946 PORTS_MODULE_ID index ,
19947 PORTS_CHANNEL channel ,
19990 PORTS_MODULE_ID index ,
19991 PORTS_CHANNEL channel ,
20031 PORTS_MODULE_ID index ,
20032 PORTS_CHANNEL channel ,
20072 PORTS_MODULE_ID index ,
20073 PORTS_CHANNEL channel ,
20117 PORTS_MODULE_ID index ,
20118 PORTS_CHANNEL channel ,
20162 PORTS_MODULE_ID index ,
20163 PORTS_CHANNEL channel ,
20209 PORTS_MODULE_ID index ,
20210 PORTS_AN_PIN anPins ,
20211 PORTS_PIN_MODE mode ) ;
20254 PORTS_MODULE_ID index ,
20255 PORTS_CN_PIN cnPins ) ;
20299 PORTS_MODULE_ID index ,
20300 PORTS_CN_PIN cnPins ) ;
20343 PORTS_MODULE_ID index ,
20344 PORTS_CN_PIN cnPins ) ;
20387 PORTS_MODULE_ID index ,
20388 PORTS_CN_PIN cnPins ) ;
20422 PORTS_MODULE_ID index ) ;
20455 PORTS_MODULE_ID index ) ;
20491 PORTS_MODULE_ID index ,
20492 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20528 PORTS_MODULE_ID index ,
20529 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20566 PORTS_MODULE_ID index ) ;
20600 PORTS_MODULE_ID index ) ;
20636 PORTS_MODULE_ID index ,
20637 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20673 PORTS_MODULE_ID index ,
20674 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20719 PORTS_MODULE_ID index ,
20720 PORTS_CHANNEL channel ,
20722 PORTS_PIN_SLEW_RATE slewRate ) ;
20759 PORTS_PIN_SLEW_RATE
20761 PORTS_MODULE_ID index ,
20762 PORTS_CHANNEL channel ,
20763 PORTS_BIT_POS bitPos ) ;
20802 PORTS_MODULE_ID index ,
20803 PORTS_CHANNEL channel ,
20804 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20837 PORTS_CHANGE_NOTICE_METHOD
20839 PORTS_MODULE_ID index ,
20840 PORTS_CHANNEL channel ) ;
20888 PORTS_MODULE_ID index ,
20889 PORTS_CHANNEL channel ,
20939 PORTS_MODULE_ID index ,
20940 PORTS_CHANNEL channel ,
20988 PORTS_MODULE_ID index ,
20989 PORTS_CHANNEL channel ,
20990 PORTS_BIT_POS bitPos ,
20991 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21034 PORTS_MODULE_ID index ,
21035 PORTS_CHANNEL channel ,
21036 PORTS_BIT_POS bitPos ) ;
21067 PORTS_MODULE_ID index ) ;
21091 PORTS_MODULE_ID index ) ;
21115 PORTS_MODULE_ID index ) ;
21139 PORTS_MODULE_ID index ) ;
21164 PORTS_MODULE_ID index ) ;
21189 PORTS_MODULE_ID index ) ;
21220 PORTS_MODULE_ID index ) ;
21248 PORTS_MODULE_ID index ) ;
21275 PORTS_MODULE_ID index ) ;
21300 PORTS_MODULE_ID index ) ;
21327 PORTS_MODULE_ID index ) ;
21352 PORTS_MODULE_ID index ) ;
21379 PORTS_MODULE_ID index ) ;
21404 PORTS_MODULE_ID index ) ;
21432 PORTS_MODULE_ID index ) ;
21460 PORTS_MODULE_ID index ) ;
21488 PORTS_MODULE_ID index ) ;
21514 PORTS_MODULE_ID index ) ;
21540 PORTS_MODULE_ID index ) ;
21566 PORTS_MODULE_ID index ) ;
21591 PORTS_MODULE_ID index ) ;
21617 PORTS_MODULE_ID index ) ;
21644 PORTS_MODULE_ID index ) ;
21669 PORTS_MODULE_ID index ) ;
21704 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21705 #define _PLIB_PORTS_COMPATIBILITY_H 21706 #include <stdint.h> 21707 #include <stddef.h> 21742 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21759 #include "system/int/sys_int.h" 21893 PORTS_MODULE_ID index ,
21894 PORTS_CHANNEL channel ) ;
21926 PORTS_MODULE_ID index ,
21927 PORTS_CHANNEL channel ,
21957 PORTS_MODULE_ID index ,
21958 PORTS_CHANNEL channel ) ;
21996 PORTS_MODULE_ID index ,
21997 PORTS_CHANNEL channel ,
22031 PORTS_MODULE_ID index ,
22032 PORTS_CHANNEL channel ,
22069 PORTS_MODULE_ID index ,
22071 PORTS_CHANNEL channel ,
22101 PORTS_MODULE_ID index ,
22102 PORTS_CHANNEL channel ) ;
22133 PORTS_MODULE_ID index ,
22134 PORTS_CHANNEL channel ,
22166 PORTS_MODULE_ID index ,
22167 PORTS_CHANNEL channel ,
22199 PORTS_MODULE_ID index ,
22200 PORTS_CHANNEL channel ,
22234 PORTS_MODULE_ID index ,
22235 PORTS_CHANNEL channel ) ;
22275 PORTS_MODULE_ID index ,
22276 PORTS_REMAP_INPUT_FUNCTION
function ,
22277 PORTS_REMAP_INPUT_PIN remapPin ) ;
22312 PORTS_MODULE_ID index ,
22313 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22314 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22347 PORTS_MODULE_ID index ) ;
22375 PORTS_MODULE_ID index ) ;
22409 PORTS_MODULE_ID index ,
22410 PORTS_CHANGE_NOTICE_PIN pinNum ,
22442 PORTS_MODULE_ID index ,
22443 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22472 PORTS_MODULE_ID index ) ;
22501 PORTS_MODULE_ID index ) ;
22532 PORTS_MODULE_ID index ,
22533 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22564 PORTS_MODULE_ID index ,
22565 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22604 PORTS_MODULE_ID index ,
22605 PORTS_ANALOG_PIN pin ,
22606 PORTS_PIN_MODE mode ) ;
22643 PORTS_MODULE_ID index ,
22644 PORTS_CHANNEL channel ,
22645 PORTS_BIT_POS bitPos ,
22680 PORTS_MODULE_ID index ,
22681 PORTS_CHANNEL channel ,
22682 PORTS_BIT_POS bitPos ) ;
22715 PORTS_MODULE_ID index ,
22716 PORTS_CHANNEL channel ,
22717 PORTS_BIT_POS bitPos ) ;
22750 PORTS_MODULE_ID index ,
22751 PORTS_CHANNEL channel ,
22752 PORTS_BIT_POS bitPos ) ;
22785 PORTS_MODULE_ID index ,
22786 PORTS_CHANNEL channel ,
22787 PORTS_BIT_POS bitPos ) ;
22820 PORTS_MODULE_ID index ,
22821 PORTS_CHANNEL channel ,
22822 PORTS_BIT_POS bitPos ) ;
22859 PORTS_MODULE_ID index ,
22861 PORTS_CHANNEL channel ,
22862 PORTS_BIT_POS bitPos ) ;
22895 PORTS_MODULE_ID index ,
22896 PORTS_CHANNEL channel ,
22897 PORTS_BIT_POS bitPos ) ;
22930 PORTS_MODULE_ID index ,
22931 PORTS_CHANNEL channel ,
22932 PORTS_BIT_POS bitPos ) ;
22965 PORTS_MODULE_ID index ,
22966 PORTS_CHANNEL channel ,
22967 PORTS_BIT_POS bitPos ) ;
23000 PORTS_MODULE_ID index ,
23001 PORTS_CHANNEL channel ,
23002 PORTS_BIT_POS bitPos ) ;
23035 PORTS_MODULE_ID index ,
23036 PORTS_CHANNEL channel ,
23037 PORTS_BIT_POS bitPos ) ;
23070 PORTS_MODULE_ID index ,
23071 PORTS_CHANNEL channel ,
23072 PORTS_BIT_POS bitPos ) ;
23105 PORTS_MODULE_ID index ,
23106 PORTS_CHANNEL channel ,
23107 PORTS_BIT_POS bitPos ,
23190 #ifndef _DRV_SPI_DEFINITIONS_H 23191 #define _DRV_SPI_DEFINITIONS_H 23197 #include <stdint.h> 23198 #include <stdbool.h> 23199 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23200 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23236 #ifndef _PLIB_SPI_H 23237 #define _PLIB_SPI_H 23271 #ifndef _PLIB_SPI_PROCESSOR_H 23272 #define _PLIB_SPI_PROCESSOR_H 23273 #error "Can't find header" 23318 SPI_MODULE_ID index ) ;
23348 SPI_MODULE_ID index ) ;
23380 SPI_MODULE_ID index ) ;
23412 SPI_MODULE_ID index ) ;
23446 SPI_MODULE_ID index ) ;
23476 SPI_MODULE_ID index ) ;
23513 SPI_MODULE_ID index ) ;
23552 SPI_MODULE_ID index ) ;
23582 SPI_MODULE_ID index ,
23613 SPI_MODULE_ID index ,
23647 SPI_MODULE_ID index ,
23648 SPI_COMMUNICATION_WIDTH width ) ;
23683 SPI_MODULE_ID index ,
23684 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23716 SPI_MODULE_ID index ,
23717 SPI_INPUT_SAMPLING_PHASE phase ) ;
23749 SPI_MODULE_ID index ,
23750 SPI_OUTPUT_DATA_PHASE phase ) ;
23781 SPI_MODULE_ID index ,
23782 SPI_CLOCK_POLARITY polarity ) ;
23812 SPI_MODULE_ID index ) ;
23842 SPI_MODULE_ID index ) ;
23880 SPI_MODULE_ID index ,
23881 uint32_t clockFrequency ,
23882 uint32_t baudRate ) ;
23913 SPI_MODULE_ID index ) ;
23945 SPI_MODULE_ID index ) ;
23978 SPI_MODULE_ID index ) ;
24011 SPI_MODULE_ID index ) ;
24043 SPI_MODULE_ID index ) ;
24073 SPI_MODULE_ID index ) ;
24104 SPI_MODULE_ID index ) ;
24135 SPI_MODULE_ID index ) ;
24166 SPI_MODULE_ID index ) ;
24198 SPI_MODULE_ID index ,
24199 SPI_FIFO_TYPE type ) ;
24231 SPI_MODULE_ID index ) ;
24263 SPI_MODULE_ID index ) ;
24297 SPI_MODULE_ID index ,
24298 SPI_FIFO_INTERRUPT mode ) ;
24328 SPI_MODULE_ID index ) ;
24358 SPI_MODULE_ID index ) ;
24390 SPI_MODULE_ID index ,
24391 SPI_FRAME_PULSE_DIRECTION direction ) ;
24424 SPI_MODULE_ID index ,
24425 SPI_FRAME_PULSE_POLARITY polarity ) ;
24458 SPI_MODULE_ID index ,
24459 SPI_FRAME_PULSE_EDGE edge ) ;
24492 SPI_MODULE_ID index ,
24493 SPI_FRAME_PULSE_WIDTH width ) ;
24527 SPI_MODULE_ID index ,
24528 SPI_FRAME_SYNC_PULSE pulse ) ;
24560 SPI_MODULE_ID index ) ;
24590 SPI_MODULE_ID index ) ;
24622 SPI_MODULE_ID index ) ;
24652 SPI_MODULE_ID index ) ;
24682 SPI_MODULE_ID index ) ;
24712 SPI_MODULE_ID index ) ;
24743 SPI_MODULE_ID index ,
24775 SPI_MODULE_ID index ,
24807 SPI_MODULE_ID index ,
24830 SPI_MODULE_ID index ) ;
24861 SPI_MODULE_ID index ,
24862 SPI_BAUD_RATE_CLOCK type ) ;
24894 SPI_MODULE_ID index ,
24895 SPI_ERROR_INTERRUPT error ) ;
24927 SPI_MODULE_ID index ,
24928 SPI_ERROR_INTERRUPT error ) ;
24959 SPI_MODULE_ID index ,
24960 SPI_AUDIO_ERROR error ) ;
24991 SPI_MODULE_ID index ,
24992 SPI_AUDIO_ERROR error ) ;
25022 SPI_MODULE_ID index ) ;
25052 SPI_MODULE_ID index ) ;
25084 SPI_MODULE_ID index ,
25085 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25117 SPI_MODULE_ID index ,
25118 SPI_AUDIO_PROTOCOL mode ) ;
25151 SPI_MODULE_ID index ) ;
25177 SPI_MODULE_ID index ) ;
25203 SPI_MODULE_ID index ) ;
25228 SPI_MODULE_ID index ) ;
25253 SPI_MODULE_ID index ) ;
25278 SPI_MODULE_ID index ) ;
25304 SPI_MODULE_ID index ) ;
25329 SPI_MODULE_ID index ) ;
25354 SPI_MODULE_ID index ) ;
25379 SPI_MODULE_ID index ) ;
25404 SPI_MODULE_ID index ) ;
25429 SPI_MODULE_ID index ) ;
25455 SPI_MODULE_ID index ) ;
25480 SPI_MODULE_ID index ) ;
25505 SPI_MODULE_ID index ) ;
25530 SPI_MODULE_ID index ) ;
25556 SPI_MODULE_ID index ) ;
25582 SPI_MODULE_ID index ) ;
25608 SPI_MODULE_ID index ) ;
25632 SPI_MODULE_ID index ) ;
25657 SPI_MODULE_ID index ) ;
25682 SPI_MODULE_ID index ) ;
25707 SPI_MODULE_ID index ) ;
25733 SPI_MODULE_ID index ) ;
25758 SPI_MODULE_ID index ) ;
25783 SPI_MODULE_ID index ) ;
25808 SPI_MODULE_ID index ) ;
25833 SPI_MODULE_ID index ) ;
25858 SPI_MODULE_ID index ) ;
25884 SPI_MODULE_ID index ) ;
25911 SPI_MODULE_ID index ) ;
25936 SPI_MODULE_ID index ) ;
25962 SPI_MODULE_ID index ) ;
25988 SPI_MODULE_ID index ) ;
26014 SPI_MODULE_ID index ) ;
26039 SPI_MODULE_ID index ) ;
26064 SPI_MODULE_ID index ) ;
26090 SPI_MODULE_ID index ) ;
26116 SPI_MODULE_ID index ) ;
26128 #include "system/common/sys_common.h" 26129 #include "system/common/sys_module.h" 26130 #include "system/int/sys_int.h" 26131 #include "system/clk/sys_clk.h" 26132 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26170 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26182 #define DRV_SPI_INDEX_0 0 26183 #define DRV_SPI_INDEX_1 1 26184 #define DRV_SPI_INDEX_2 2 26185 #define DRV_SPI_INDEX_3 3 26186 #define DRV_SPI_INDEX_4 4 26187 #define DRV_SPI_INDEX_5 5 26199 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26448 SPI_MODULE_ID
spiId ;
26481 CLK_BUSES_PERIPHERAL
spiClk ;
26641 const SYS_MODULE_INDEX index ,
26642 const SYS_MODULE_INIT *
const init ) ;
26684 SYS_MODULE_OBJ
object ) ;
26733 SYS_MODULE_OBJ
object ) ;
26774 SYS_MODULE_OBJ
object ) ;
26839 const SYS_MODULE_INDEX drvIndex ,
27434 #include "driver/usb/usbhs/drv_usbhs.h" 27463 #include <stdint.h> 27483 uint8_t RevNumber ;
27570 SYS_MODULE_OBJ sysTmr ;
27571 SYS_MODULE_OBJ drvTmr0 ;
27572 SYS_MODULE_OBJ drvTmr1 ;
27573 SYS_MODULE_OBJ drvTmr2 ;
27574 SYS_MODULE_OBJ drvTmr3 ;
27575 SYS_MODULE_OBJ drvTmr4 ;
27576 SYS_MODULE_OBJ drvUsart0 ;
27577 SYS_MODULE_OBJ drvPMP0 ;
27579 SYS_MODULE_OBJ spiObjectIdx0 ;
27581 SYS_MODULE_OBJ spiObjectIdx1 ;
27583 SYS_MODULE_OBJ spiObjectIdx2 ;
27584 SYS_MODULE_OBJ drvUSBObject ;
27585 SYS_MODULE_OBJ usbDevObject0 ;
27745 #include <stdbool.h> 27746 #include <stdint.h> 27752 #define FIFO_RX_SIZE 7 27753 #define FIFO_TX_SIZE 7 27755 #define FIFO_ADD_OK 0 27756 #define FIFO_FULL 1 27758 #define FIFO_EMPTY 2U 27769 uint8_t * ptr_buffer ;
27774 uint8_t num_records ;
27775 uint8_t put_error ;
27776 uint8_t get_error ;
27817 uint8_t * ptrBuffer ,
27818 uint16_t Length ) ;
27905 TFifo * ptrFifo ) ;
27930 TFifo * ptrFifo ) ;
27965 #include <stdbool.h> 27966 #include <stdint.h> 27998 uint8_t bitposn ) ;
28024 uint8_t bitposn ) ;
28118 #include <stdbool.h> 28119 #include <stdint.h> 28160 uint8_t command [ 7 ] ;
28161 bool process_complete_flag ;
28162 bool b_command_complete_flag ;
28163 bool sw_status_bit_check ;
28397 #include "../system_definitions.h" 28438 bool write_complete ;
28442 uint8_t bytes_received ;
28566 #include <stdint.h> 28567 #include <stdbool.h> 28568 #include <stddef.h> 28569 #include <stdlib.h> 28570 #include "system_config.h" 28571 #include "system_definitions.h" 28613 USB_DEVICE_HANDLE usbDevHandle ;
28614 bool deviceIsConfigured ;
28615 uint8_t configValue ;
28617 bool epDataWritePending ;
28618 bool epDataReadPending ;
28619 USB_DEVICE_TRANSFER_HANDLE writeTranferHandle ;
28620 USB_DEVICE_TRANSFER_HANDLE readTranferHandle ;
28621 USB_ENDPOINT_ADDRESS endpointTx ;
28622 USB_ENDPOINT_ADDRESS endpointRx ;
28623 uint8_t altSetting ;
28624 uint8_t byte_count ;
28699 #include <stdbool.h> 28746 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28865 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 19)));
28886 int zzqqzs = ((int)(
bitmapstruct.element2 |= (1 << 21)));
28911 int zzqqzs = ((int)(
bitmapstruct.element2 |= (1 << 26)));
28927 #define qqqbranches 94 28928 #define QQQMAXMCDCSIZE 2 28932 #define ldra_sscanf 28948 #undef qqnull_params 28949 #define qqnull_params void 28951 #define qqzzidfield 1 28957 #define QQQFIXEDSIZE 28977 qqcptr = qqscan_str;
28979 while (qqcptr[0] ==
' ')
28985 if (qqcptr[0] ==
'-')
28991 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
28993 qqvalue = 10 * qqvalue;
28994 qqvalue = qqvalue + (qqcptr[0] -
'0');
28997 qqvalue = qqisign * qqvalue;
29023 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
29024 ldra_port_write (&ldra_buffer[0]);
29032 ldra_port_write(s);
29040 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
29041 ldra_port_write (&ldra_buffer[0]);
29049 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
29050 ldra_port_write (&ldra_buffer[0]);
29058 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
29059 ldra_port_write (&ldra_buffer[0]);
29178 static int branches_printed = 0;
29182 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
29183 ldra_port_write (&ldra_buffer[0]);
29184 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
29185 ldra_port_write (&ldra_buffer[0]);
29187 branches_printed += 8;
29207 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 29208 #define LASTELEMENT 29209 #include "commmodule_53zbelem.def"
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
uintptr_t DRV_USART_BUFFER_HANDLE
void DRV_TMR2_PeriodValueSet(uint32_t value)
static void qqoutput0(FILEPOINT char *s)
static void DRV_TMR1_Tasks(void)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void DRV_TMR2_Initialize(void)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
SPI_BAUD_RATE_CLOCK baudClockSource
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
SYS_ERROR_LEVEL gblErrLvl
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void DRV_TMR_Stop(DRV_HANDLE handle)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool DRV_TMR2_Start(void)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
bool DRV_TMR0_Start(void)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_IC0_Initialize(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
static void Fifo_Init(TFifo *ptrFifo, uint8_t *ptrBuffer, uint16_t Length)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
static void qqqbitmapreset(qqnull_params)
static SYS_STATUS DRV_TMR4_Status(void)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR1_PeriodValueSet(uint32_t value)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
uint32_t DRV_TMR4_PeriodValueGet(void)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
void DRV_ADC_DeInitialize(void)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
void DRV_PMP0_Write(uint8_t data)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
void DRV_TMR1_StopInIdleEnable(void)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
void DRV_USART_Close(const DRV_HANDLE handle)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void DRV_USART0_TasksTransmit(void)
static void DRV_TMR1_DeInitialize(void)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
static int qqqqbmselwidth
void DRV_TMR0_CounterClear(void)
bool DRV_TMR3_Start(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
uint8_t jobQueueReserveSize
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
SYS_MODULE_INIT moduleInit
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool DRV_SPIn_TransmitterBufferIsFull(void)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
uint32_t DRV_TMR2_CounterValueGet(void)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
uint8_t Fifo_Length(TFifo *ptrFifo)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
static int commmodule_53zqzqzq(int qqqi)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
static int qqqisinitialised
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
static int commmodule_53zqendz(int qqqi)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void DRV_TMR3_PeriodValueSet(uint32_t value)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
INT_SOURCE txInterruptSource
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
static SYS_STATUS DRV_TMR3_Status(void)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void DRV_USART0_WriteByte(const uint8_t byte)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
void DRV_USART0_TasksError(void)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
uint32_t DRV_TMR0_CounterValueGet(void)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
static void DRV_TMR4_DeInitialize(void)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool DRV_IC0_BufferIsEmpty(void)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
static void DRV_TMR4_Tasks(void)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
DRV_USART_TRANSFER_STATUS
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void DRV_TMR1_StopInIdleDisable(void)
void DRV_TMR3_Initialize(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
static void ValidateComm(void)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void DRV_ADC1_Close(void)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
void SYS_DEBUG_Message(const char *message)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SYS_DMA_CHANNEL_CHAIN_PRIO
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
void DRV_ADC_Initialize(void)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
static void qqoutput(FILEPOINT char *s, int i)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
uint16_t DRV_IC0_Capture16BitDataRead(void)
static unsigned char qqqzzglobflag
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
void DRV_IC_Stop(DRV_HANDLE handle)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR4_CounterValueGet(void)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
static void DRV_TMR0_DeInitialize(void)
void Prepare_Return_B(uint8_t byt [])
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
#define DRV_IC_Close(handle)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR4_StopInIdleDisable(void)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
#define commmodule_53zzopen
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR4_Close(void)
bool DRV_TMR_Start(DRV_HANDLE handle)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
SYS_STATUS DRV_USART0_Status(void)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void Set_Status(uint8_t bitposn)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
static void ReadUART(void)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
static SYS_STATUS DRV_TMR1_Status(void)
static COMM_STATES C_STATES
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint32_t DRV_TMR3_CounterValueGet(void)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool DRV_USART0_TransmitBufferIsFull(void)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
uint32_t DRV_TMR3_PeriodValueGet(void)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
bool DRV_SPIn_ReceiverBufferIsFull(void)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR1_Open(void)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
uint32_t SYS_DMA_ChannelCRCGet(void)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
static void DRV_TMR3_Tasks(void)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
DRV_USART_BAUD_SET_RESULT
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
static void DRV_TMR0_Close(void)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
uint8_t DRV_USART0_ReadByte(void)
bool DRV_TMR1_Start(void)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
static int commmodule_53zqqzqz(qqnull_params)
uint8_t Fifo_Put(TFifo *ptrFifo, uint8_t Data)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
static void qqqqinitialise(int ii)
void qqqtotalupload(void)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
static int commmodule_53zscanf(char *qqscan_str)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR1_PeriodValueGet(void)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
static void Execute_Protocol_B(void)
void DRV_TMR0_StopInIdleDisable(void)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
void DRV_PMP0_ModeConfig(void)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
static void Execute_Auto_Protocol_A(void)
static void qqoutput2(FILEPOINT char *s, int i, int j)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
static SYS_STATUS DRV_TMR0_Status(void)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Execute_System(void)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
CLK_BUSES_PERIPHERAL spiClk
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
uint8_t Fifo_Get(TFifo *ptrFifo)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
void PLIB_USART_Enable(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
ldra_void_function qqqaccumupload[QQQnumfil]
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
SPI_COMMUNICATION_WIDTH commWidth
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
uint8_t DRV_PMP0_Read(void)
static void DRV_TMR0_Tasks(void)
void SYS_DMA_Suspend(void)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void DRV_TMR4_StopInIdleEnable(void)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void DRV_TMR2_Open(void)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void DRV_TMR4_CounterClear(void)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_TMR0_PeriodValueSet(uint32_t value)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void DRV_TMR2_CounterValueSet(uint32_t value)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void APP_Initialize(void)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
void DRV_USART0_Close(void)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
static void DRV_TMR2_Close(void)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_ADC0_Close(void)
uint32_t DRV_TMR0_PeriodValueGet(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
void DRV_PMP0_Initialize(void)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
struct _DRV_SPI_INIT DRV_SPI_INIT
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void DRV_SPI_Close(DRV_HANDLE handle)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
uint32_t DRV_IC0_Capture32BitDataRead(void)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
void DRV_TMR0_StopInIdleEnable(void)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
static void DRV_TMR0_Open(void)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
void SYS_PORTS_Initialize()
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
void DRV_TMR2_StopInIdleEnable(void)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void DRV_TMR2_CounterClear(void)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DEBUG_Print(const char *format,...)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
static void DRV_TMR3_DeInitialize(void)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
void DRV_TMR3_StopInIdleDisable(void)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
#define commmodule_53zqqzqz1
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_USART0_Deinitialize(void)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
static void DRV_TMR3_Open(void)
void PLIB_USART_Disable(USART_MODULE_ID index)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
static void DRV_TMR3_Close(void)
uintptr_t DRV_SPI_BUFFER_HANDLE
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
void DRV_TMR4_Initialize(void)
SPI_AUDIO_PROTOCOL audioProtocolMode
DRV_SPI_CLOCK_MODE clockMode
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_TMR4_PeriodValueSet(uint32_t value)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
void DRV_TMR1_CounterValueSet(uint32_t value)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool GetDepthStatus(void)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
static void usb_watchdog(void)
void DRV_TMR_Close(DRV_HANDLE handle)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
static void DRV_TMR4_Open(void)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint32_t DRV_TMR1_CounterValueGet(void)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void Clear_Status(uint8_t bitposn)
DRV_USART_TRANSFER_STATUS
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
INT_SOURCE rxInterruptSource
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
void DRV_TMR1_Initialize(void)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR0_Initialize(void)
static SYS_STATUS DRV_TMR2_Status(void)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
INT_SOURCE errInterruptSource
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
ldra_void_function qqqaccumreset[QQQnumfil]
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void DRV_TMR2_StopInIdleDisable(void)
uint32_t DRV_TMR2_PeriodValueGet(void)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
bool Valid_Command(uchar8_t msg)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_DMA_Resume(void)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
void DRV_TMR0_CounterValueSet(uint32_t value)
SYS_DMA_CHANNEL_IGNORE_MATCH
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
DRV_SPI_TASK_MODE taskMode
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Execute_Protocol_A(void)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
static void DRV_TMR2_DeInitialize(void)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool process_complete_flag
static void DRV_TMR1_Close(void)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
bool DRV_TMR4_Start(void)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
void(* ldra_void_function)()
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
#define DRV_IC_Open(drvIndex, intent)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
void DRV_TMR4_CounterValueSet(uint32_t value)
void DRV_TMR3_CounterValueSet(uint32_t value)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void DRV_TMR3_CounterClear(void)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
void DRV_TMR3_StopInIdleEnable(void)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
SPI_FRAME_SYNC_PULSE frameSyncPulse
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void DRV_USART0_TasksReceive(void)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
static void qqqupload(qqnull_params)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
static int qqqstructzzopen
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
void DRV_TMR1_CounterClear(void)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
bool SYS_DMA_IsBusy(void)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
static void WriteUART(void)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)